1. Field of the Invention
This invention relates to computers, and more particularly to a control system and its method of operation for controlling the execution speed of a computer to permit it to operate with circuits having binary switching speeds slower than the computer circuit switching speed.
2. Description of Related Art
Variable cycle time microcomputers are known in the prior art. U.S. Pat. No. 4,509,120 shows a device for use with a microcomputer. The device is arranged with a parameter latch register for storing a binary value representing a desired access cycle delay. The delay is accomplished by forcing the microprocessor to the not ready state, thereby providing additional time for a device to respond to a write or read command. The parameter latch register is adapted to receive the binary value, either during manufacture or during the execution of instructions.
Likewise, U.S. Pat. No. 4,050,096 provides pulse expansion for microprocessor systems with slow memory. Logic circuitry expands the clock pulse which is applied to the microprocessor chip whenever a memory location is addressed which has a longer access time than is consistent with the width of the pulse ordinarily supplied to the microprocessor. Also, it is known to operate at different sampling rates when communicating over different communication lines U.S Pat. No. 3,909,971 shows such a system.